1. Field of the Invention
The present invention relates to memory systems, and more particularly, to a memory system capable of programming multi-bit data. The invention also relates to programming methods for such memory systems.
This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2007-0000737, filed on Jan. 3, 2007, the subject matter of which is hereby incorporated by reference.
2. Discussion of Related Art
An increasing number of consumer products use nonvolatile memory to store data. Examples of contemporary consumer products incorporating nonvolatile memory include MP3 players, digital cameras, mobile phones, camcorders, flash cards, and solid-state disks (SSDs).
As the variety and sophistication of these consumer products increases, nonvolatile memory is expected to store an increasing quantity of data and to access this data at faster speeds. One approach to increasing the overall data storage capacity of nonvolatile memory is the use of the multi-level cell (MLC). In contrast to conventional single-level cells (SLC), multi-level memory cells are able to store more than one data bit per cell.
Figure (FIG.) 1 is a general block diagram of a conventional memory system. The conventional memory system 100 includes a host processor (e.g., a CPU) 110, a memory controller 120, and flash memory 130.
Memory controller 120 includes a buffer memory 121. Flash memory 130 includes a cell array 131 and a page buffer 132. Although not illustrated in FIG. 1, flash memory 130 also includes a decoder, a data buffer, and a control unit.
Memory controller 120 receives data and a corresponding write command from host 110 and controls flash memory 130, such that the data is written in cell array 131. Alternately, memory controller 120 receives a read command from host 110 and controls flash memory 130, such that data indicated by the read command is read from cell array 131.
Buffer memory 121 is used within memory controller 120 to temporarily store “write data” to be written to flash memory 130 or “read data” retrieved from flash memory 130. Under the control of memory controller 120, buffer memory 121 transfers this temporarily-stored read/write data to host 110 or flash memory 130.
Cell array 131 of flash memory 130 includes a plurality of memory cells arranged in an array. The memory cells are nonvolatile and are therefore able to retain stored data even in the absence of applied power. Page buffer 132 stores write data to be written to a selected page in cell array 131 or read data retrieved from a selected page.
The constituent memory cells of flash memory 130 may be single-level cells or multi-level cells. An example of flash memory 130 will first be described under an assumption that single-level memory cells are used.
A SLC has two possible data states (1 or 0) depending on threshold voltage distributions. A SLC storing a logical value of “1” is in an erase state. A SLC storing a logical value of “0” is in a program state. The erase-state memory cell is referred to as an ON cell, and the program-state memory cell is referred to as an OFF cell.
Flash memory 130 performs a program operation on a page-by-page basis. During the program operation, memory controller 120 transfers write data to flash memory 130 on a page-by-page basis through buffer memory 121.
Page buffer 132 temporarily stores the write data received from buffer memory 121, and then programs the loaded write data into a selected memory page. Upon completion of the program operation, a program verifying operation is performed to verify that the data has been correctly programmed.
If a program failure occurs, the program operation and corresponding program verifying operation are again performed after increasing the voltage used to program the selected page. In this way, a program operation for a given page of write data may be successfully completed. Thereafter, a next batch of write data is received and the program operation is repeated.
A second description of the operation of flash memory 130 will now be given under the assumption that multi-level cells are used. FIG. 2 is a voltage threshold diagram illustrating a process of programming the least significant bit (LSB) and the most significant bit (MSB) of a 2-bit MLC. Two bit multi-level memory cells are used in the following descriptions, but the invention is not limited to only 2-bit memory cells. Within this context, LSB and MSB designations are clear. Alternately stated, however, any “first bit” and “second bit” arrangement might be used beyond the MSB and LSB relationship apparent in a 2-bit memory cell.
Referring to FIG. 2, a MLC is programmed to have one of four states 11, 01, 10 and 00 according its threshold voltage distribution. The LSB is programmed in a process similar to that of the SLC. A memory cell with a state 11 is programmed to have a state A (indicated by a dashed line) according to its LSB of data.
Thereafter, memory controller 120 transfers a page of write data from buffer memory 121 to flash memory 130 in order to program the MSB. Referring to FIG. 2, a MLC having state A is programmed to have a state 00 or a state 10 according to its MSB of data. On the other hand, a memory cell having a state 11 is programmed to either maintain the state 11 or to have a state 01 according to its MSB of data.
Thus, the program operation for a MLC proceeds in two distinct stages. That is, the LSB is first programmed in the MLC and then the MSB is programmed.
However, a program failure may occur during the programming of the MSB independent of the previously performed LSB programming operation. Fortunately, damaged MSB data may be repaired because “current” MSB data is retained in buffer memory 121 until completion of a corresponding, program verifying operation.
Unfortunately, experience has shown that MSB programming errors frequently change previously-programmed LSB data. However, damaged LSB data cannot be repaired as simply as damaged MSB data, since the (earlier stage) LSB data is no longer stored in buffer memory 121. Therefore, conventional flash memory systems incorporating multi-level cells are prone to the loss of LSB data.